WebAssembly SIMD conversion instructions

Converts the lanes of a v128 f64x2 value interpretation into a signed i32x4 value interpretation.

Converts the lanes of a v128 f64x2 value interpretation into an unsigned i32x4 value interpretation.

Converts the lanes of a v128 f32x4 value interpretation into a signed i32x4 value interpretation.

Converts the lanes of a v128 f32x4 value interpretation into an unsigned i32x4 value interpretation.

Converts the lanes of a v128 f64x2 value interpretation into an f32x4 value interpretation. The two higher lanes of the result are initialized to zero.

Converts the first two lanes of a v128 f32x4 value interpretation into an f64x2 value interpretation.

Replaces the specified lane of a v128 value interpretation with a new value and returns the resulting v128 value interpretation.

Returns a new v128 value interpretation with its lane values selected from two input v128 values, determined by provided index values.

Copies the same value to all lanes of a v128 value interpretation.

Returns a new v128 value interpretation with its lane values selected from an input v128 value, determined by indices provided in a second input v128.

Rounds the value in each lane of a v128 value interpretation up to the nearest integer above.

Rounds the value in each lane of a v128 value interpretation down to the nearest integer below.

Rounds the value in each lane of a v128 value interpretation to the nearest integer towards zero.

Performs a saturating conversion of the lanes of a v128 f32x4 value interpretation into a signed i32x4 value interpretation.

Performs a saturating conversion of the lanes of a v128 f32x4 value interpretation into an unsigned i32x4 value interpretation.

Performs a saturating conversion of the lanes of a v128 f64x2 value interpretation into a signed i32x4 value interpretation. The two higher lanes of the result are initialized to zero.

Performs a saturating conversion of the lanes of a v128 f64x2 value interpretation into an unsigned i32x4 value interpretation. The two higher lanes of the result are initialized to zero.